1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the semiconductor device.
2. Description of Related Art
In recent years, a strain channel technology for improving device performance by applying strain to a channel region is used for a miniaturized field effect transistor (FET).
It has heretofore been well known that performance is improved by applying a uniaxial tensile strain in a source/drain direction to a channel region in the case of an n-type FET and a uniaxial compressive strain in a source/drain direction to a channel region in the case of a p-type FET. On this occasion, it is expected that the application of a stronger strain yields better device performance.
As a method for introducing uniaxial strain in a source/drain direction, a method for forming a stress applying film so as to cover the upper plane of an FET is generally used and a structure of introducing different stress applying films to n-type and p-type FETs respectively is proposed (H. S. Yang et al., “Dual Stress Liner for High Performance sub-45 nm Gate Length SOI CMOS Manufacturing”, 2004 International Electron Devices Meeting Technical Digest, The Institute of Electrical and Electronics Engineers, Inc., 1075-1078 (2004)).
Further, when a structure of protruding a source/drain region is used, proposed is a structure of bringing a stress applying film close to a channel region by etching a gate sidewall insulating film and forming a space between the source/drain region and a gate region in order to enhance strain generated in the channel region by the stress applying film (International Publication No. 2007/077748).
Furthermore, it is also reported that, in a metal-substituted gate process, stress applied to a channel is enhanced by removing a stress applying film formed over the upper parts of a dummy gate electrode and a gate electrode after the stress applying film is formed (S. Yamakawa et al., “Study of Stress Effect on Replacement Gate Technology with Compressive Stress Liner and eSiGe for pFETs”, Proceedings of 2008 International Conference on Simulation of Semiconductor Processes and Devices, The Institute of Electrical and Electronics Engineers, Inc., 109-112 (2008)).